layouted further

This commit is contained in:
Empire 2023-10-16 01:10:03 +02:00
parent 33082b7481
commit fd08921bba
4 changed files with 54637 additions and 52161 deletions

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@ -1,6 +1,6 @@
{
"board": {
"active_layer": 36,
"active_layer": 1,
"active_layer_preset": "",
"auto_track_width": false,
"hidden_netclasses": [],
@ -68,7 +68,7 @@
39,
40
],
"visible_layers": "ffcffff_ffffffff",
"visible_layers": "fffffff_ffffffff",
"zone_display_mode": 0
},
"meta": {

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@ -45,7 +45,7 @@
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
"min_clearance": 0.508
"min_clearance": 0.0
}
},
"diff_pair_dimensions": [
@ -176,7 +176,9 @@
0.0,
0.2,
0.5,
1.0
1.0,
1.5,
2.0
],
"via_dimensions": [
{
@ -403,7 +405,7 @@
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"pin_to_pin": "error",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "ignore",
@ -425,7 +427,7 @@
"classes": [
{
"bus_width": 12,
"clearance": 0.2,
"clearance": 0.15,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
@ -449,30 +451,13 @@
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "5V",
"name": "High_Current",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 1.4,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Mini",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgb(255, 4, 6)",
"track_width": 1.0,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6
"wire_width": 39
},
{
"bus_width": 12,
@ -483,13 +468,30 @@
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Power",
"name": "Medium_Current",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 1.7,
"schematic_color": "rgb(251, 255, 0)",
"track_width": 0.5,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6
"wire_width": 20
},
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Signal",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgb(21, 255, 3)",
"track_width": 0.2,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 8
}
],
"meta": {
@ -945,6 +947,14 @@
{
"netclass": "Default",
"pattern": "VCC_FUSED_ALWAYS"
},
{
"netclass": "High_Current",
"pattern": "12V"
},
{
"netclass": "High_Current",
"pattern": "/12VR"
}
]
},

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