fix rtc storage
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@@ -2,8 +2,9 @@
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use core::cell::RefCell;
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use core::mem::{self, MaybeUninit};
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use std::convert::Infallible;
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use crate::hal::digital::v2::OutputPin;
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use hal::digital::OutputPin;
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trait ShiftRegisterInternal {
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fn update(&self, index: usize, command: bool) -> Result<(), ()>;
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@@ -24,16 +25,18 @@ impl<'a> ShiftRegisterPin<'a> {
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}
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}
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impl OutputPin for ShiftRegisterPin<'_> {
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type Error = ();
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impl embedded_hal::digital::ErrorType for ShiftRegisterPin<'_> {
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type Error = Infallible;
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}
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fn set_low(&mut self) -> Result<(), Self::Error> {
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self.shift_register.update(self.index, false)?;
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impl OutputPin for ShiftRegisterPin<'_> {
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fn set_low(&mut self) -> Result<(), Infallible> {
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self.shift_register.update(self.index, false).unwrap();
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Ok(())
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}
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fn set_high(&mut self) -> Result<(), Self::Error> {
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self.shift_register.update(self.index, true)?;
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fn set_high(&mut self) -> Result<(), Infallible> {
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self.shift_register.update(self.index, true).unwrap();
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Ok(())
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}
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}
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