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This commit is contained in:
Empire
2024-01-07 14:33:02 +01:00
parent 5724088780
commit a30dbe0759
12 changed files with 1205 additions and 763 deletions
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58
rust/src/sipo.rs
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@@ -10,21 +10,21 @@ trait ShiftRegisterInternal {
}
/// Output pin of the shift register
pub struct ShiftRegisterPin<'a>
{
pub struct ShiftRegisterPin<'a> {
shift_register: &'a dyn ShiftRegisterInternal,
index: usize,
}
impl<'a> ShiftRegisterPin<'a>
{
impl<'a> ShiftRegisterPin<'a> {
fn new(shift_register: &'a dyn ShiftRegisterInternal, index: usize) -> Self {
ShiftRegisterPin { shift_register, index }
ShiftRegisterPin {
shift_register,
index,
}
}
}
impl OutputPin for ShiftRegisterPin<'_>
{
impl OutputPin for ShiftRegisterPin<'_> {
type Error = ();
fn set_low(&mut self) -> Result<(), Self::Error> {
@@ -42,9 +42,10 @@ macro_rules! ShiftRegisterBuilder {
($name: ident, $size: expr) => {
/// Serial-in parallel-out shift register
pub struct $name<Pin1, Pin2, Pin3>
where Pin1: OutputPin,
Pin2: OutputPin,
Pin3: OutputPin
where
Pin1: OutputPin,
Pin2: OutputPin,
Pin3: OutputPin,
{
clock: RefCell<Pin1>,
latch: RefCell<Pin2>,
@@ -53,12 +54,13 @@ macro_rules! ShiftRegisterBuilder {
}
impl<Pin1, Pin2, Pin3> ShiftRegisterInternal for $name<Pin1, Pin2, Pin3>
where Pin1: OutputPin,
Pin2: OutputPin,
Pin3: OutputPin
where
Pin1: OutputPin,
Pin2: OutputPin,
Pin3: OutputPin,
{
/// Sets the value of the shift register output at `index` to value `command`
fn update(&self, index: usize, command: bool) -> Result<(), ()>{
fn update(&self, index: usize, command: bool) -> Result<(), ()> {
self.output_state.borrow_mut()[index] = command;
let output_state = self.output_state.borrow();
self.latch.borrow_mut().set_low().map_err(|_e| ())?;
@@ -78,11 +80,11 @@ macro_rules! ShiftRegisterBuilder {
}
}
impl<Pin1, Pin2, Pin3> $name<Pin1, Pin2, Pin3>
where Pin1: OutputPin,
Pin2: OutputPin,
Pin3: OutputPin
where
Pin1: OutputPin,
Pin2: OutputPin,
Pin3: OutputPin,
{
/// Creates a new SIPO shift register from clock, latch, and data output pins
pub fn new(clock: Pin1, latch: Pin2, data: Pin3) -> Self {
@@ -95,14 +97,12 @@ macro_rules! ShiftRegisterBuilder {
}
/// Get embedded-hal output pins to control the shift register outputs
pub fn decompose(&self) -> [ShiftRegisterPin; $size] {
pub fn decompose(&self) -> [ShiftRegisterPin; $size] {
// Create an uninitialized array of `MaybeUninit`. The `assume_init` is
// safe because the type we are claiming to have initialized here is a
// bunch of `MaybeUninit`s, which do not require initialization.
let mut pins: [MaybeUninit<ShiftRegisterPin>; $size] = unsafe {
MaybeUninit::uninit().assume_init()
};
let mut pins: [MaybeUninit<ShiftRegisterPin>; $size] =
unsafe { MaybeUninit::uninit().assume_init() };
// Dropping a `MaybeUninit` does nothing, so if there is a panic during this loop,
// we have a memory leak, but there is no memory safety issue.
@@ -117,12 +117,16 @@ macro_rules! ShiftRegisterBuilder {
/// Consume the shift register and return the original clock, latch, and data output pins
pub fn release(self) -> (Pin1, Pin2, Pin3) {
let Self{clock, latch, data, output_state: _} = self;
let Self {
clock,
latch,
data,
output_state: _,
} = self;
(clock.into_inner(), latch.into_inner(), data.into_inner())
}
}
}
};
}
ShiftRegisterBuilder!(ShiftRegister8, 8);
@@ -143,4 +147,4 @@ ShiftRegisterBuilder!(ShiftRegister120, 120);
ShiftRegisterBuilder!(ShiftRegister128, 128);
/// 8 output serial-in parallel-out shift register
pub type ShiftRegister<Pin1, Pin2, Pin3> = ShiftRegister8<Pin1, Pin2, Pin3>;
pub type ShiftRegister<Pin1, Pin2, Pin3> = ShiftRegister8<Pin1, Pin2, Pin3>;